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## Project    : Ultrascale FPGA Gen3 Integrated Block for PCI Express
## File       : xdma_x8gen3_pcie3_ip_ooc.xdc
## Version    : 4.4 
##-----------------------------------------------------------------------------
#
# This constraints file contains default clock frequencies to be used during out-of-context flows such as
# OOC Synthesis and Hierarchical Designs. For best results the frequencies should be modified
# to match the target frequencies. 
# This constraints file is not used in normal top-down synthesis (the default flow of Vivado)
#

create_clock -name sys_clk -period 10 [get_ports sys_clk]
create_clock -name sys_clk_gt -period 10 [get_ports sys_clk_gt]
#
set_case_analysis 1 [get_nets  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/PHY_TXOUTCLKSEL[2]}] 
set_case_analysis 0 [get_nets  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/PHY_TXOUTCLKSEL[1]}]  
set_case_analysis 1 [get_nets  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/PHY_TXOUTCLKSEL[0]}]
#
# Set Divide By 2
set_case_analysis 1 [get_pins  -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells   -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells   -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells   -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_userclk}]]
# Set Divide By 2
set_case_analysis 1 [get_pins  -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_pclk}]]
# Set Divide By 4
set_case_analysis 1 [get_pins  -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/bufg_mcap_clk}]]
set_case_analysis 1 [get_pins  -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/bufg_mcap_clk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/bufg_mcap_clk}]]
# Set Divide By 1
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[0]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[1]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk}]]
set_case_analysis 0 [get_pins  -filter {REF_PIN_NAME=~DIV[2]} -of_objects [get_cells  -hierarchical -filter {NAME =~ *xdma_x8gen3_pcie3_ip_gt_top_i/phy_clk_i/bufg_gt_coreclk}]]
#
 
